Direct Transistor-Level Layout for Digital Blocks

Direct Transistor-Level Layout for Digital Blocks
Автор
 
Год
 
Страниц
 
180
ISBN
 
1402076657
Издатель
 
Cisco Press
Категория
 
Новинки Интеллекта

Содержание:

Парадоски, Провенансы, Куклы, Конспекты по Мерабу, Из летних записей, Танго, День рождения, Раздоры, Истрия, Рыбки-прилипалы, Невстреча, Мне снился сон, Таксистка, Песнь натурщицы, Спор суфиев, Вуду, Вместо интервью, Профессионалы, Главный герой, Колыбельная, Реквием, Карамзиндеревенский дневник, Гордневник

Описание:

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and...

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