Source-Level Debugging of VHDL Designs
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Описание:
As design density and complexity of digital systems increase, the costs due to design faults increase exponentially. Therefore, detecting, localizing, and correcting faults are crucial issues in today`s fast-paced and fault-prone development process. Test case generation and verification tools detect faults and provide the user with a failing run. Even with a detailed failing run in hand, locating and correcting a fault is a bland and time-consuming chore. Debugging, which is the process of locating and correcting a fault, is not done solely by designers. The verification engineers, the ones who write and run the verification tests, usually spend quite a lot of their own time analyzing the failure traces themselves. Debugging is one of the most time consuming tasks in the effort to improve system quality. It takes 50 to 80 percent of the time used for verification depending on the level of automation of the verification tools. Fault localization may significantly reduce design cycle...Похожие книги
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